There is a phenomenon called cache thrashing, where data in a certain cache line within cache memory is frequently overwritten. As a related art technique, for example, a technique that profiles an application by using a performance monitor in order to collect cache miss data, and inserts preload instructions prior to effective address positions of offending instructions that create long cache misses is disclosed. A technique in which it is determined whether or not the deterioration of the performance ascribable to the deterioration of the cache use efficiency is small even when the array is subjected to the padding is disclosed. A technique of adding run-time prediction code for cache misses within a loop is disclosed. The code predicts at run time, on a per loop basis on which prefetch is performed, whether or not the cache miss ratio of a loop will be greater than or equal to a certain threshold. A technique is disclosed in which, after aligned loop decomposition is performed, scheduling for executing small loops included in the same data localizable group (DLG) continuously as long as possible is performed, and the layout change using padding is made for array data used in each DLG. As examples of the related art, Japanese Laid-open Patent Publication No. 2000-035894, Japanese Laid-open Patent Publication No. 2011-128803, Japanese Laid-open Patent Publication No. 10-207772, and Japanese Laid-open Patent Publication No. 2004-252728 are disclosed.
However, according to the related art techniques, it is difficult to inhibit cache thrashing from occurring while a program is running. For example, even when, as a result of analysis performed by using a performance monitor, it is detected that cache thrashing would occur, and padding is added, analysis and program execution will be repeated a plurality of times in order to check whether or not cache thrashing is in reality inhibited from occurring. In view of the above, it is desirable that cache thrashing be inhibited from occurring while a program is running.